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1 of 54 november 28, 2011 ? 2011 integrated device technology, inc. ? idt and the idt logo are registered trademarks of integrated device technology, inc. device overview the 89HPES34H16G2 is a member of the idt precise? family of pci express? switching solutions. the pes34h16g2 is a 34-lane, 16- port peripheral chip that performs pci express packet switching with a feature set optimized for high-performance applications such as servers, storage, and communications/network ing. it provides connectivity and switching functions between a pci express upstream port and up to fifteen downstream ports and supports switching between downstream ports. features ? high performance non-blocking switch architecture ? 34-lane 16-port pcie switch ? three x8 switch ports each of which can bifurcate to two x4 ports (total of six x4 ports) ? ten x1 switch ports ? integrated serdes supports 5.0 gt/s gen2 and 2.5 gt/s gen1 operation ? delivers up to 34 gbps (272 gbps) of switching capacity ? supports 128 bytes to 2 kb maximum payload size ? low latency cut-through architecture ? supports one virtual channel and eight traffic classes ? standards and compatibility ? pci express base specification 2.0 compliant ? implements the following optional pci express features ? advanced error reporting (aer) on all ports ? end-to-end crc (ecrc) ? access control services (acs) ? power budgeting enhanced capability ? device serial number enhanced capability ? sub-system id and sub-system vendor id capability ? internal error reporting ecn ? multicast ecn ? vga and isa enable ? l0s and l1 aspm ?ari ecn ? compatible with idt 89hpes34h16 pcie gen1 switch ? port configurability ? x8, x4, and x1 ports ? ability to merge adjacent x4 ports to create a x8 port ? automatic per port link width negotiation (x8 x4 x2 x1) ? crosslink support ? automatic lane reversal ? autonomous and software managed link width and speed control ? per lane serdes configuration ? de-emphasis ? receive equalization ? drive strength ? switch partitioning ? idt proprietary feature that creates logically independent switches in the device ? supports up to 16 fully independent switch partitions ? configurable downstream port device numbering ? supports dynamic reconfiguration of switch partitions ? dynamic port reconfigurati on (downstream or upstream) ? dynamic migration of ports between partitions ? movable upstream port within and between switch partitions ? initialization / configuration ? supports root (bios, os, or driver), serial eeprom, or smbus switch initialization ? common switch configurations are supported with pin strap- ping (no external components) ? supports in-system serial eeprom initialization/program- ming ? quality of service (qos) ? port arbitration ? round robin ? request metering ? idt proprietary feature that balances bandwidth among switch ports for maximum system throughput ? high performance switch core architecture ? combined input output queued (cioq) switch architecture with large buffers ? multicast ? compliant to the pci-sig multicast ecn ? supports arbitrary multicasting of posted transactions ? supports 64 multicast groups ? multicast overlay mechanism support ? ecrc regeneration support ? clocking ? supports 100 mhz and 125 mhz reference clock frequencies ? flexible clocking modes ? common clock ? non-common clock ? hot-plug and hot swap ? hot-plug controller on all ports ? hot-plug supported on all downstream switch ports 89HPES34H16G2 data sheet 34-lane 16-port pcie? gen2 system interconnect switch
2 of 54 november 28, 2011 idt 89HPES34H16G2 data sheet ? all ports support hot-plug using low-cost external i 2 c i/o expanders ? configurable presence detect supports card and cable appli- cations ? gpe output pin for hot-plug event notification ? enables sci/smi generation for legacy operating system support ? hot-swap capable i/o ? power management ? supports d0, d3hot and d3 power management states ? active state power management (aspm) ? supports l0, l0s, l1, l2/l3 ready and l3 link states ? configurable l0s and l1 entry timers allow performance/ power-savings tuning ? supports pci express power budgeting capability ? serdes power savings ? supports low swing / half-swing serdes operation ? serdes optionally turned-off in d3hot ? serdes associated with unused ports are turned-off ? serdes associated with unused lanes are placed in a low power state ? 32 general purpose i/o ? reliability, availability and serviceability (ras) ? ecrc support ? aer on all ports ? secded ecc protection on all internal rams ? end-to-end data path parity protection ? checksum serial eeprom content protected ? autonomous link reliability (preserves system operation in the presence of faulty links) ? ability to generate an interrupt (intx or msi) on link up/down transitions ? test and debug ? on-chip link activity and status outputs available for port 0 (upstream port) ? per port link activity and status outputs available using external i 2 c i/o expander for all other ports ? serdes test modes ? supports ieee 1149.6 ac jtag and ieee 1149.1 jtag ? power supplies ? requires only two power supply voltages (1.0 v and 2.5 v) note that a 3.3v is preferred for v dd i/o ? no power sequencing requirements ? packaged in a 35mm x 35mm 1156-ball flip chip bga with 1mm ball spacing ? compatible with idt 89hpes34h16 pcie gen1 switch note: for pin compatibility issues, contact the idt help desk at ssdhelp@idt.com . product description utilizing standard pci express interconnect, the pes34h16g2 provides the most efficient i/o connectivity for applications requiring high throughput, low latency, and simple board layout with a minimum number of board layers. it provides 34 gbps (272 gbps) of aggregated, full-duplex switching capacity through 34 integrated serial lanes, using proven and robust idt technology. each lane provides 5 gt/s of band- width in both directions and is fully compliant with pci express base specification, revision 2.0. the pes34h16g2 is based on a flexible and efficient layered archi- tecture. the pci express layer consists of serdes, physical, data link and transaction layers. the pes34h16g2 can operate either as a store and forward switch or a cut-through switch. it supports eight traffic classes (tcs) and one virtual channel (vc) with sophisticated resource management to enable efficient switching and i/o connectivity. the pes34h16g2 is a partitionable pcie switch. this means that in addition to operating as a standard pci express switch, the pes34h16g2 ports may be partitioned into groups that logically operate as completely independent pcie switches. figure 2 illustrates a three partition pes34h16g2 configuration.
3 of 54 november 28, 2011 idt 89HPES34H16G2 data sheet block diagram figure 1 pes34h16g2 block diagram figure 2 example of usage of switch partitioning 34 pci express lanes up to 6 x4 ports and 10 x1 ports 16-port switch core frame buffer route table port arbitration scheduler dl/transaction layer serdes x8/x4/x2/x1 dl/transaction layer serdes x1 dl/transaction layer serdes x1 dl/transaction layer serdes x8/x4/x2/x1 (10) dl/transaction layer serdes x8/x4/x2/x1 . . . . partition 1 ? virtual pci bus p2p bridge partition 1 upstream port p2p bridge p2p bridge p2p bridge p2p bridge partition 2 ? virtual pci bus p2p bridge p2p bridge p2p bridge partition 3 ? virtual pci bus p2p bridge p2p bridge p2p bridge partition 1 downstream ports partition 2 downstream ports partition 3 downstream ports partition 2 upstream port partition 3 upstream port
4 of 54 november 28, 2011 idt 89HPES34H16G2 data sheet smbus interface the pes34h16g2 contains two smbus interfaces . the slave interface provides full access to the configuration registers in the pe s34h16g2, allowing every configuration register in the device to be read or written by an external agent. the master interface allows the default configuration register values of the pes34h16g2 to be overridden following a rese t with values programmed in an external serial eeprom. the m aster interface is also used by an external hot-plug i/o expander. six pins make up each of the two smbus interfaces. these pins consist of an smbus clock pin, an smbus data pin, and 4 smbus add ress pins. in the slave interface, these address pins allow the smbus address to which the device responds to be configured. in the master in terface, these address pins allow the smbus address of the serial configuration eeprom from which data is loaded to be configured. the smbus a ddress is set up on negation of perstn by sampling the corresponding address pins. when the pins are sampled, the resulting address is assigned as shown in table 1. as shown in figure 3, the master and slave smbu ses may only be used in a split configuration. figure 3 split smbus interface configuration the switch?s smbus master interface does not support smbus arbitrat ion. as a result, the switch?s smbus master must be the only master in the smbus lines that connect to the serial eeprom and i/o expander slav es. in the split configuration, the master and slave smbuses operate as two independent buses; thus, multi-master arbitration is not required. bit slave smbus address master smbus address 1 ssmbaddr[1] msmbaddr[1] 2 ssmbaddr[2] msmbaddr[2] 3 ssmbaddr[3] msmbaddr[3] 4 0 msmbaddr[4] 5 ssmbaddr[5] 1 61 0 71 1 table 1 master and slave smbus address assignment processor switch ssmbclk ssmbdat msmbclk msmbdat smbus master other smbus devices serial eeprom ... hot-plug i/o expander
5 of 54 november 28, 2011 idt 89HPES34H16G2 data sheet hot-plug interface the pes34h16g2 supports pci express hot-plug on each downstream por t (ports 1 through 15). to reduce the number of pins require d on the device, the pes34h16g2 utilizes an external i/o expander, such as that used on pc motherboards, connected to the smbus master i nterface. following reset and configuration, whenever the state of a ho t-plug output needs to be modified, the pes34h16g2 generates an sm bus transaction to the i/o expander with the new value of all of the output s. whenever a hot-plug input changes, the i/o expander generates an interrupt which is received on the ioexpintn input pin (alternate function of gpio) of the pes34h16g2. in response to an i/o expander interrupt, t he pes34h16g2 generates an smbus transaction to read the state of all of the hot-plug inputs from the i/o expander. general purpose input/output the pes34h16g2 provides 32 general purpose i/o (gpio) pins that may be individually configured as general purpose inputs, gener al purpose outputs, or alternate functions. some gpio pins are shared wi th other on-chip functions. these alternate functions may be enabl ed via software, smbus slave interface, or serial configuration eeprom. pin description the following tables list the functions of the pins provided on the pes34h16g2. some of the functions listed may be multiplexed onto the same pin. the active polarity of a signal is defined using a suff ix. signals ending with an ?n? are defined as being active, or asse rted, when at a logic zero (low) level. all other signals (including clocks, buses, and select lines) will be interpreted as being active, or asserted, wh en at a logic one (high) level. differential signals end with a suffix ?n? or ?p.? the different ial signal ending in ?p? is the positive portion of the differe ntial pair and the differential signal ending in ?n? is the negative porti on of the differential pair. signal type name/description pe00rn[3:0] pe00rp[3:0] i pci express port 0 serial data receive. differential pci express receive pairs for port 0. pe00tn[3:0] pe00tp[3:0] o pci express port 0 serial data transmit. differential pci express transmit pairs for port 0. pe01rn[3:0] pe01rp[3:0] i pci express port 1 serial data receive. differential pci express receive pairs for port 1. when port 0 is merged with port 1, these signals become port 0 receive pairs for lanes 4 through 7. pe01tn[3:0] pe01tp[3:0] o pci express port 1 serial data transmit. differential pci express transmit pairs for port 1. when port 0 is merged with port 1, these signals become port 0 transmit pairs for lanes 4 through 7. pe02rn[3:0] pe02rp[3:0] i pci express port 2 serial data receive. differential pci express receive pairs for port 2. pe02tn[3:0] pe02tp[3:0] o pci express port 2 serial data transmit. differential pci express transmit pairs for port 2. pe03rn[3:0] pe03rp[3:0] i pci express port 3 serial data receive. differential pci express receive pairs for port 3. when port 2 is merged with port 3, these signals become port 2 receive pairs for lanes 4 through 7. pe03tn[3:0] pe03tp[3:0] o pci express port 3 serial data transmit. differential pci express transmit pairs for port 2. when port 2 is merged with port 3, these signals become port 2 transmit pairs for lanes 4 through 7. pe04rn[3:0] pe04rp[3:0] i pci express port 4 serial data receive. differential pci express receive pairs for port 4. pe04tn[3:0] pe04tp[3:0] o pci express port 4 serial data transmit. differential pci express transmit pairs for port 4. pe05rn[3:0] pe05rp[3:0] i pci express port 5 serial data receive. differential pci express receive pairs for port 5. when port 4 is merged with port 5, these signals become port 4 receive pairs for lanes 4 through 7. table 2 pci express interface pins (part 1 of 2)
6 of 54 november 28, 2011 idt 89HPES34H16G2 data sheet pe05tn[3:0] pe05tp[3:0] o pci express port 5 serial data transmit. differential pci express transmit pairs for port 5. when port 4 is merged with port 5, these signals become port 4 transmit pairs for lanes 4 through 7. pe06rn[0] pe06rp[0] i pci express port 6 serial data receive. differential pci express receive pair for port 6. pe06tn[0] pe06tp[0] o pci express port 6 serial data transmit. differential pci express transmit pair for port 6. pe07rn[0] pe07rp[0] i pci express port 7 serial data receive. differential pci express receive pair for port 7. pe07tn[0] pe07tp[0] o pci express port 7 serial data transmit. differential pci express transmit pair for port 7. pe08rn[0] pe08rp[0] i pci express port 8 serial data receive. differential pci express receive pair for port 8. pe08tn[0] pe08tp[0] o pci express port 8 serial data transmit. differential pci express transmit pair for port 8. pe09rn[0] pe09rp[0] i pci express port 9 serial data receive. differential pci express receive pair for port 9. pe09tn[[0] pe09tp[0] o pci express port 9 serial data transmit. differential pci express transmit pair for port 9. pe10rn[0] pe10rp[0] i pci express port 10 serial data receive. differential pci express receive pair for port 10. pe10tn[0] pe10tp[0] o pci express port 10 serial data transmit. differential pci express transmit pair for port 10. pe11rn[0] pe11rp[0] i pci express port 11 serial data receive. differential pci express receive pair for port 11. pe11tn[0] pe11tp[0] o pci express port 11 serial data transmit. differential pci express transmit pair for port 11. pe12rn[0] pe12rp[0] i pci express port 12 serial data receive. differential pci express receive pair for port 12. pe12tn[0] pe12tp[0] o pci express port 12 serial data transmit. differential pci express transmit pair for port 12. pe13rn[0] pe13rp[0] i pci express port 13 serial data receive. differential pci express receive pair for port 13. pe13tn[0] pe13tp[0] o pci express port 13 serial data transmit. differential pci express transmit pair for port 13. w pe14rn[0] pe14rp[0] i pci express port 14 serial data receive. differential pci express receive pair for port 14. pe14tn[0] pe14tp[0] o pci express port 14 serial data transmit. differential pci express transmit pair for port 14. pe15rn[0] pe15rp[0] i pci express port 15 serial data receive. differential pci express receive pair for port 15. pe15tn[0] pe15tp[0] o pci express port 15 serial data transmit. differential pci express transmit pair for port 15. signal type name/description table 2 pci express interface pins (part 2 of 2)
7 of 54 november 28, 2011 idt 89HPES34H16G2 data sheet signal type name/description gclkn[1:0] gclkp[1:0] i global reference clock. differential reference clock input pair. this clock is used as the reference clock by on-chip plls to generate the clocks required for the system logic. the frequency of the differential reference clock is determined by the gclkfsel signal. table 3 reference clock pins signal type name/description msmbaddr[4:1] i master smbus address. these pins determine the smbus address of the serial eeprom from which configuration information is loaded. msmbclk i/o master smbus clock. this bidirectional signal is used to synchronize transfers on the master smbus. it is active and generating the clock only when the eeprom or i/o expanders are being accessed. msmbdat i/o master smbus data. this bidirectional signal is used for data on the master smbus. ssmbaddr[5,3:1] i slave smbus address. these pins determine the smbus address to which the slave smbus interface responds. ssmbclk i/o slave smbus clock. this bidirectional signal is used to synchronize transfers on the slave smbus. ssmbdat i/o slave smbus data. this bidirectional signal is used for data on the slave smbus. table 4 smbus interface pins signal type name/description gpio[0] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. alternate function pin name: part0perstn alternate function pin type: input/output alternate function: assertion of this signal initiated a partition fundamental reset in the corresponding partition. gpio[1] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. alternate function pin name: part1perstn alternate function pin type: input/output alternate function: assertion of this signal initiated a partition fundamental reset in the corresponding partition. gpio[2] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. alternate function pin name: part2perstn alternate function pin type: input/output alternate function: assertion of this signal initiated a partition fundamental reset in the corresponding partition. gpio[3] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. alternate function pin name: part3perstn alternate function pin type: input/output alternate function: assertion of this signal initiated a partition fundamental reset in the corresponding partition. table 5 general purpose i/o pins (part 1 of 5)
8 of 54 november 28, 2011 idt 89HPES34H16G2 data sheet gpio[4] i general purpose i/o. this pin can be configured as a general purpose i/o pin. 1st alternate function ? reserved 2nd alternate function pin name: p0linkupn 2nd alternate function pin type: output 2nd alternate function: port 0 link up status output. gpio[5] o general purpose i/o. this pin can be configured as a general purpose i/o pin. 1st alternate function pin name: gpen 1st alternate function pin type: output 1st alternate function: hot-plug general purpose even output. 2nd alternate function pin name: p0activen 2nd alternate function pin type: output 2nd alternate function: port 0 link active status output. gpio[6] i general purpose i/o. this pin can be configured as a general purpose i/o pin. gpio[7] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. gpio[8] i general purpose i/o. this pin can be configured as a general purpose i/o pin. alternate function pin name: ioexpintn alternate function pin type: input alternate function: io expander interrupt. gpio[9] i general purpose i/o. this pin can be configured as a general purpose i/o pin. alternate function pin name: hp0apn alternate function pin type: input alternate function: hot plug signal group 0 attention push button input. gpio[10] i general purpose i/o. this pin can be configured as a general purpose i/o pin. alternate function pin name: hp0pdn alternate function pin type: input alternate function: hot plug signal group 0 presence detect input. gpio[11] i general purpose i/o. this pin can be configured as a general purpose i/o pin. alternate function pin name: hp0pfn alternate function pin type: input alternate function: hot plug signal group 0 power fault input. gpio[12] i general purpose i/o. this pin can be configured as a general purpose i/o pin. alternate function pin name: hp0pwrgdn alternate function pin type: input alternate function: hot plug signal group 0 power good input. gpio[13] i general purpose i/o. this pin can be configured as a general purpose i/o pin. alternate function pin name: hp0mrln alternate function pin type: input alternate function: hot plug signal group 0 manually operated retention latch input. gpio[14] o general purpose i/o. this pin can be configured as a general purpose i/o pin. alternate function pin name: hp0ain alternate function pin type: output alternate function: hot plug signal group 0 attention indicator output. signal type name/description table 5 general purpose i/o pins (part 2 of 5)
9 of 54 november 28, 2011 idt 89HPES34H16G2 data sheet gpio[15] o general purpose i/o. this pin can be configured as a general purpose i/o pin. alternate function pin name: hp0pin alternate function pin type: output alternate function: hot plug signal group 0 power indicator output. gpio[16] o general purpose i/o. this pin can be configured as a general purpose i/o pin. alternate function pin name: hp0pep alternate function pin type: output alternate function: hot plug signal group 0 power enable output. gpio[17] o general purpose i/o. this pin can be configured as a general purpose i/o pin. alternate function pin name: hp0rstn alternate function pin type: output alternate function: hot plug signal group 0 reset output. gpio[18] i general purpose i/o. this pin can be configured as a general purpose i/o pin. alternate function pin name: hp1apn alternate function pin type: input alternate function: hot plug signal group 1 attention push button input. gpio[19] i general purpose i/o. this pin can be configured as a general purpose i/o pin. alternate function pin name: hp1pdn alternate function pin type: input alternate function: hot plug signal group 1 presence detect input. gpio[20] i general purpose i/o. this pin can be configured as a general purpose i/o pin. alternate function pin name: hp1pfn alternate function pin type: input alternate function: hot plug signal group 1 power fault input. gpio[21] i general purpose i/o. this pin can be configured as a general purpose i/o pin. alternate function pin name: hp1pwrgdn alternate function pin type: input alternate function: hot plug signal group 1 power good input. gpio[22] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. 1st alternate function pin name: hp1mrln 1st alternate function pin type: input 1st alternate function: hot plug signal group 1 manually operated reten- tion. 2nd alternate function pin name: p1linkupn 2nd alternate function pin type: output 2nd alternate function: port 1 link up status output. gpio[23] o general purpose i/o. this pin can be configured as a general purpose i/o pin. 1st alternate function pin name: hp1ain 1st alternate function pin type: output 1st alternate function: hot plug signal group 1 attention indicator output. 2nd alternate function pin name: p1activen 2nd alternate function pin type: output 2nd alternate function: port 1 link active status output. signal type name/description table 5 general purpose i/o pins (part 3 of 5)
10 of 54 november 28, 2011 idt 89HPES34H16G2 data sheet gpio[24] o general purpose i/o. this pin can be configured as a general purpose i/o pin. 1st alternate function pin name: hp1pin 1st alternate function pin type: output 1st alternate function: hot plug signal group 1 power indicator output. 2nd alternate function pin name: p2linkupn 2nd alternate function pin type: output 2nd alternate function: port 2 link up status output. gpio[25] o general purpose i/o. this pin can be configured as a general purpose i/o pin. 1st alternate function pin name: hp1pep 1st alternate function pin type: output 1st alternate function: hot plug signal group 1 power enable output. 2nd alternate function pin name: p2activen 2nd alternate function pin type: output 2nd alternate function: port 2 link active status output. gpio[26] o general purpose i/o. this pin can be configured as a general purpose i/o pin. 1st alternate function pin name: hp1rstn 1st alternate function pin type: output 1st alternate function: hot plug signal group 1 reset output. 2nd alternate function pin name: p3linkupn 2nd alternate function pin type: output 2nd alternate function: port 3 link up status output. gpio[27] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. 1st alternate function pin name: hp2apn 1st alternate function pin type: input 1st alternate function: hot plug signal group 2 attention push button input. 2nd alternate function pin name: p3activen 2nd alternate function pin type: output 2nd alternate function: port 3 link active status output. gpio[28] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. 1st alternate function pin name: hp2pdn 1st alternate function pin type: input 1st alternate function: hot plug signal group 0 presence detect input. 2nd alternate function pin name: p4linkupn 2nd alternate function pin type: output 2nd alternate function: port 4 link up status output. signal type name/description table 5 general purpose i/o pins (part 4 of 5)
11 of 54 november 28, 2011 idt 89HPES34H16G2 data sheet gpio[29] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. 1st alternate function pin name: hp2pfn 1st alternate function pin type: input 1st alternate function: hot plug signal group 2 power fault input. 2nd alternate function pin name: p4activen 2nd alternate function pin type: output 2nd alternate function: port 4 link active status output. gpio[30] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. 1st alternate function pin name: hp2pwrgdn 1st alternate function pin type: input 1st alternate function: hot plug signal group 2 power good input. 2nd alternate function pin name: p5linkupn 2nd alternate function pin type: output 2nd alternate function: port 5 link up status output. gpio[31] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. 1st alternate function pin name: hp2mrln 1st alternate function pin type: input 1st alternate function: hot plug signal group 2 manually operated reten- tion latch input. 2nd alternate function pin name: p5activen 2nd alternate function pin type: output 2nd alternate function: port 5 link active status output. signal type name/description clkmode[1:0] clock mode. these signals determine the port clocking mode used by ports of the device. gclkfsel i global clock frequency select. these signals select the frequency of the gclkp and gclkn signals. 0x0 100 mhz 0x1 125 mhz msmbsmode i master smbus slow mode. the assertion of this pin indicates that the master smbus should operate at 100 khz instead of 400 khz. this value may not be overridden. p01mergen i port 0 and 1 merge. p01mergen is an active low signal. it is pulled low internally. when this pin is low, port 0 is merged with port 1 to form a single x8 port. the serdes lanes associated with port 1 become lanes 4 through 7 of port 0. when this pin is high, port 0 and port 1 are not merged, and each operates as a single x4 port. p23mergen i port 2 and 3 merge. p23mergen is an active low signal. it is pulled low internally. when this pin is low, port 2 is merged with port 3 to form a single x8 port. the serdes lanes associated with port 3 become lanes 4 through 7 of port 2. when this pin is high, port 2 and port 3 are not merged, and each operates as a single x4 port. p45mergen i port 4 and 5 merge. p45mergen is an active low signal. it is pulled low internally. when this pin is low, port 4 is merged with port 5 to form a single x8 port. the serdes lanes associated with port 5 become lanes 4 through 7 of port 4. when this pin is high, port 4 and port 5 are not merged, and each operates as a single x4 port. table 6 system pins (part 1 of 2) signal type name/description table 5 general purpose i/o pins (part 5 of 5)
12 of 54 november 28, 2011 idt 89HPES34H16G2 data sheet perstn i fundamental reset. assertion of this signal resets all logic inside the pes34h16g2 and initiates a pci express fundamental reset. rsthalt i reset halt. when this signal is asserted during a pci express fundamental reset, the pes34h16g2 executes the reset procedure and remains in a reset state with the mas- ter and slave smbuses active. this allows software to read and write registers internal to the device before normal device operation begins. the device exits the reset state when the rsthalt bit is cleared in the pa_swctl register by an smbus master. swmode[3:0] i switch mode. these configuration pi ns determine the pes34h16g2 switch operating mode. note: these pins should be static and not change following the negation of perstn. 0x0 - single partition 0x1 - single partiti on with serial eeprom initialization 0x2 through 0x7 - reserved 0x8 - single partition with port 0 selected as the upstream port (port 2 disabled) 0x9 - single partition with port 2 selected as the upstream port (port 0 disabled) 0xa - single partition with serial eeprom initialization and port 0 selected as the upstream port (port 2 disabled) 0xb - single partition with serial eeprom initialization and port 2 selected as the upstream port (port 0 disabled) 0xc - multi-partition 0xd - multi-partition with serial eeprom initialization 0xe - reserved 0xf - reserved signal type name/description jtag_tck i jtag clock . this is an input test clock used to clock the shifting of data into or out of the boundary scan logic or jtag controller. jtag_tck is independent of the system clock with a nominal 50% duty cycle. jtag_tdi i jtag data input . this is the serial data input to the boundary scan logic or jtag controller. jtag_tdo o jtag data output . this is the serial data shifted out from the boundary scan logic or jtag controller. when no data is being shifted out, this signal is tri-stated. jtag_tms i jtag mode . the value on this signal controls the test mode select of the boundary scan logic or jtag controller. jtag_trst_n i jtag reset . this active low signal asynchronously resets the boundary scan logic and jtag tap controller. an external pull-up on the board is recommended to meet the jtag specification in cases where the tester can access this signal. however, for systems running in functional mode, one of the following should occur: 1) actively drive this signal low with control logic 2) statically drive this signal low with an external pull-down on the board table 7 test pins signal type name/description table 6 system pins (part 2 of 2)
13 of 54 november 28, 2011 idt 89HPES34H16G2 data sheet signal type name/description refres00 i/o port 0 external reference resistor. provides a reference for the port 0 serdes bias currents and pll calibration circuitry. a 3 kohm +/- 1% resis- tor should be connected from this pin to ground. refres01 i/o port 1 external reference resistor. provides a reference for the port 1 serdes bias currents and pll calibration circuitry. a 3 kohm +/- 1% resis- tor should be connected from this pin to ground. refres02 i/o port 2 external reference resistor. provides a reference for the port 2 serdes bias currents and pll calibration circuitry. a 3 kohm +/- 1% resis- tor should be connected from this pin to ground. refres30 i/o port 3 external reference resistor. provides a reference for the port 3 serdes bias currents and pll calibration circuitry. a 3 kohm +/- 1% resis- tor should be connected from this pin to ground. refres04 i/o port 4 external reference resistor. provides a reference for the port 4 serdes bias currents and pll calibration circuitry. a 3 kohm +/- 1% resis- tor should be connected from this pin to ground. refres05 i/o port 5 external reference resistor. provides a reference for the port 5 serdes bias currents and pll calibration circuitry. a 3 kohm +/- 1% resis- tor should be connected from this pin to ground. refres06 i/o port 6 external reference resistor. provides a reference for the port 6 serdes bias currents and pll calibration circuitry. a 3 kohm +/- 1% resis- tor should be connected from this pin to ground. refres07 i/o port 7 external reference resistor. provides a reference for the port 7 serdes bias currents and pll calibration circuitry. a 3 kohm +/- 1% resis- tor should be connected from this pin to ground. refres08 i/o port 8 external reference resistor. provides a reference for the port 8 serdes bias currents and pll calibration circuitry. a 3 kohm +/- 1% resis- tor should be connected from this pin to ground. refres09 i/o port 9 external reference resistor. provides a reference for the port 9 serdes bias currents and pll calibration circuitry. a 3 kohm +/- 1% resis- tor should be connected from this pin to ground. refres10 i/o port 10 external reference resistor. provides a reference for the port 10 serdes bias currents and pll calibration circuitry. a 3 kohm +/- 1% resis- tor should be connected from this pin to ground. refres11 i/o port 11 external reference resistor. provides a reference for the port 11 serdes bias currents and pll calibration circuitry. a 3 kohm +/- 1% resis- tor should be connected from this pin to ground. refres12 i/o port 12 external reference resistor. provides a reference for the port 12 serdes bias currents and pll calibration circuitry. a 3 kohm +/- 1% resis- tor should be connected from this pin to ground. refres13 i/o port 13 external reference resistor. provides a reference for the port 13 serdes bias currents and pll calibration circuitry. a 3 kohm +/- 1% resis- tor should be connected from this pin to ground. refres14 i/o port 14 external reference resistor. provides a reference for the port 14 serdes bias currents and pll calibration circuitry. a 3 kohm +/- 1% resis- tor should be connected from this pin to ground. table 8 power, ground, and serdes resistor pins (part 1 of 2)
14 of 54 november 28, 2011 idt 89HPES34H16G2 data sheet refres15 i/o port 15 external reference resistor. provides a reference for the port 15 serdes bias currents and pll calibration circuitry. a 3 kohm +/- 1% resis- tor should be connected from this pin to ground. refrespll i/o pll external reference resistor. provides a reference for the pll bias currents and pll calibration circuitry. a 3k ohm +/- 1% resistor should be connected from this pin to ground. v dd core i core v dd. power supply for core logic (1.0v). v dd i/o i i/o v dd. lvttl i/o buffer power supply (2.5v or preferred 3.3v). v dd pea i pci express analog power. serdes analog power supply (1.0v). v dd peha i pci express analog high power. serdes analog power supply (2.5v). v dd peta i pci express transmitter analog voltage. serdes transmitter analog power supply (1.0v). v ss i ground. signal type name/description table 8 power, ground, and serdes resistor pins (part 2 of 2)
15 of 54 november 28, 2011 idt 89HPES34H16G2 data sheet pin characteristics note: some input pads of the switch do not contain internal pull-ups or pull-downs. unused smbus and system inputs should be tied off to appropriate levels. this is especially critical for unused contro l signal inputs which, if left floating, could adversely affec t operation. also, floating pins can cause a slight increase in power consumption. unused serdes (rx and tx) pi ns should be left floating. finally, no conn ection pins should not be connected. function pin name type buffer i/o type internal resistor 1 notes pci express interface pe00rn[3:0] i pcie differential 2 serial link pe00rp[3:0] i pe00tn[3:0] o pe00tp[3:0] o pe01rn[3:0] i pe01rp[3:0] i pe01tn[3:0] o pe01tp[3:0] o pe02rn[3:0] i pe02rp[3:0] i pe02tn[3:0] o pe02tp[3:0] o pe03rn[3:0] i pe03rp[3:0] i pe03tn[3:0] o pe03tp[3:0] o pe04rn[3:0] i pe04rp[3:0] i pe04tn[3:0] o pe04tp[3:0] o pe05rn[3:0] i pe05rp[3:0] i pe05tn[3:0] o pe05tp[3:0] o pe06rn[0] i pe06rp[0] i pe06tn[0] o pe06tp[0] o pe07rn[0] i pe07rp[0] i pe07tn[0] o pe07tp[0] o pe08rn[0] i table 9 pin characteristics (part 1 of 4)
16 of 54 november 28, 2011 idt 89HPES34H16G2 data sheet pci express interface (cont.) pe08rp[0] i pcie differential serial link pe08tn[0] o pe08tp[0] o pe09rn[0] i pe09rp[0] i pe09tn[0] o pe09tp[0] o pe10rn[0] i pe10rp[0] i pe10tn[0] o pe10tp[0] o pe11rn[0] i pe11rp[0] i pe11tn[0] o pe11tp[0] o pe12rn[0] i pe12rp[0] i pe12tn[0] o pe12tp[0] o pe13rn[0] i pe13rp[0] i pe13tn[0] o pe13tp[0] o pe14rn[0] i pe14rp[0] i pe14tn[0] o pe14tp[0] o pe15rn[0] i pe15rp[0] i pe15tn[0] o pe15tp[0] o gclkn[1:0] i hcsl diff. clock input refer to table 10 gclkp[1:0] i function pin name type buffer i/o type internal resistor 1 notes table 9 pin characteristics (part 2 of 4)
17 of 54 november 28, 2011 idt 89HPES34H16G2 data sheet smbus msmbaddr[4:1] i lvttl pull-down msmbclk i/o sti 3 msmbdat i/o sti ssmbaddr[5,3:1] i pull-up ssmbclk i/o sti ssmbdat i/o sti general purpose i/o gpio[31:0] i/o lvttl pull-up system pins clkmode[1:0] i lvttl input pull-up gclkfsel i pull-down msmbsmode i pull-down p01mergen i pull-down p23mergen i pull-down p45mergen i pull-down perstn i sti rsthalt i input pull-down swmode[3:0] i pull-down ejtag / jtag jtag_tck i lvttl sti pull-up jtag_tdi i sti pull-up jtag_tdo o jtag_tms i sti pull-up jtag_trst_n i sti pull-up external pull-down serdes reference resis- tors refres00 i/o analog refres01 i/o refres02 i/o refres03 i/o refres04 i/o refres05 i/o refres06 i/o refres07 i/o refres08 i/o refres09 i/o refres10 i/o refres11 i/o refres12 i/o refres13 i/o function pin name type buffer i/o type internal resistor 1 notes table 9 pin characteristics (part 3 of 4)
18 of 54 november 28, 2011 idt 89HPES34H16G2 data sheet serdes reference resis- tors (cont.) refres14 i/o analog refres15 i/o refrespll i/o 1. internal resistor values under typical operating conditions are 92k for pull-up and 91k for pull-down. 2. all receiver pins set the dc common mode voltage to ground. all transmitters must be ac coupled to the media. 3. schmitt trigger input (sti). function pin name type buffer i/o type internal resistor 1 notes table 9 pin characteristics (part 4 of 4)
19 of 54 november 28, 2011 idt 89HPES34H16G2 data sheet logic diagram ? pes34h16g2 figure 4 pes34h16g2 logic diagram jtag_tck gpio[31:0] 32 general purpose i/o msmbaddr[4:1] msmbclk msmbdat 4 master smbus interface jtag_tdi jtag_tdo jtag_tms jtag_trst_n jtag pins pe00rp[0] pe00rn[0] pe00rp[3] pe00rn[3] pe00tp[0] pe00tn[0] pe00tp[3] pe00tn[3] ... ... pe01rp[0] pe01rn[0] pe01rp[3] pe01rn[3] pcie switch serdes input pe01tp[0] pe01tn[0] pe01tp[3] pe01tn[3] ... port 1 ... pe02rp[0] pe02rn[0] pe02rp[3] pe02rn[3] pe02tp[0] pe02tn[0] pe02tp[3] pe02tn[3] ... ... pe05rp[0] pe05rn[0] pe05rp[3] pe05rn[3] pe05tp[0] pe05tn[0] pe05tp[3] pe05tn[3] ... ... pe06rp[0] pe06rn[0] pe15rp[0] pe15rn[0] pcie switch serdes input pe06tp[0] pe06tn[0] pe15tp[0] pe15tn[0] pcie switch serdes output ... port 15 port 15 ... pes34h16g2 ... ssmbaddr[5,3:1] ssmbclk ssmbdat 4 slave smbus interface pcie switch serdes input port 6 pcie switch serdes input port 5 pcie switch serdes input port 2 pcie switch serdes input port 0 pcie switch serdes output port 6 pcie switch serdes output port 1 pcie switch serdes output port 0 pcie switch serdes output port 2 pcie switch serdes output port 5 ... global reference clocks gclkn[1:0] gclkp[1:0] gclkfsel v dd core v dd i/o v dd pea power/ground v ss v dd peha v dd peta rsthalt system pins swmode[3:0] 4 clkmode[1:0] perstn 2 p01mergen p23mergen msmbsmode p45mergen serdes reference resistors refrespll refres[15:0]
20 of 54 november 28, 2011 idt 89HPES34H16G2 data sheet system clock parameters values based on systems running at recommended supply voltages and operating temperatures, as shown in tables 14 and 15. ac timing characteristics parameter description condition min typical max unit refclk freq input reference clock frequency range 100 125 1 1. the input clock frequency will be either 100 or 125 mhz depending on signal gclkfsel . mhz t c-rise rising edge rate differential 0.6 4 v/ns t c-fall falling edge rate differential 0.6 4 v/ns v ih differential input high voltage differential +150 mv v il differential input low voltage differential -150 mv v cross absolute single-ended crossing point voltage single-ended +250 +550 mv v cross-delta variation of v cross over all rising clock edges single-ended +140 mv v rb ring back voltage margin differential -100 +100 mv t stable time before v rb is allowed differential 500 ps t period-avg average clock period accuracy -300 2800 ppm t period-abs absolute period, including spread-spec- trum and jitter 9.847 10.203 ns t cc-jitter cycle to cycle jitter 150 ps v max absolute maximum input voltage +1.15 v v min absolute minimum input voltage -0.3 v duty cycle duty cycle 40 60 % rise/fall matching single ended rising refclk edge rate ver- sus falling refclk edge rate 20 % z c-dc clock source output dc impedance 40 60 table 10 input clock requirements parameter description gen 1 gen 2 units min 1 typ 1 max 1 min 1 typ 1 max 1 pcie transmit ui unit interval 399.88 400 400.12 199.94 200 200.06 ps t tx-eye minimum tx eye width 0.75 0.75 ui t tx-eye-median-to- max-jitter maximum time between the jitter median and maximum deviation from the median 0.125 ui t tx-rise , t tx-fall tx rise/fall time: 20% - 80% 0.125 0.15 ui t tx- idle-min minimum time in idle 20 20 ui table 11 pcie ac timing characteristics (part 1 of 2)
21 of 54 november 28, 2011 idt 89HPES34H16G2 data sheet figure 5 gpio ac timing waveform t tx-idle-set-to-idle maximum time to transition to a valid idle after sending an idle ordered set 88 ns t tx-idle-to-diff- data maximum time to transition from valid idle to diff data 8 8 ns t tx-skew transmitter data skew between any 2 lanes 1.3 1.3 ns t min-pulsed minimum instantaneous lone pulse width na 0.9 ui t tx-hf-dj-dd transmitter deterministic jitter > 1.5mhz bandwidth na 0.15 ui t rf-mismatch rise/fall time differential mismatch na 0.1 ui pcie receive ui unit interval 399.88 400 400.12 199.94 200.06 ps t rx-eye (with jitter) minimum receiver eye width (jitter tolerance) 0.4 0.4 ui t rx-eye-medium to max jitter max time between jitter median & max deviation 0.3 ui t rx-skew lane to lane input skew 20 8 ns t rx-hf-rms 1.5 ? 100 mhz rms jitter (common clock) na 3.4 ps t rx-hf-dj-dd maximum tolerable dj by the receiver (common clock) na 88 ps t rx-lf-rms 10 khz to 1.5 mhz rms jitter (common clock) na 4.2 ps t rx-min-pulse minimum receiver instantaneous eye width na 0.6 ui 1. minimum, typical, and maximum values meet the requirements under pci specification 2.0 signal symbol reference edge min max unit timing diagram reference gpio gpio[31:0] 1 1. gpio signals must meet the setup and hold times if they are synchronous or the minimum pulse width if they are asynchronous. tpw_13b 2 2. the values for this symbol were determined by calculation, not by testing. none 50 ? ns see figure 5. table 12 gpio ac timing characteristics parameter description gen 1 gen 2 units min 1 typ 1 max 1 min 1 typ 1 max 1 table 11 pcie ac timing characteristics (part 2 of 2) tpw_13b extclk gpio (asynchronous input)
22 of 54 november 28, 2011 idt 89HPES34H16G2 data sheet figure 6 jtag ac timing waveform signal symbol reference edge min max unit timing diagram reference jtag jtag_tck tper_16a none 50.0 ? ns see figure 6. thigh_16a, tlow_16a 10.0 25.0 ns jtag_tms 1 , jtag_tdi 1. the jtag specification, ieee 1149.1, recommends that jtag_tms should be held at 1 while the signal applied at jtag_trst_n changes from 0 to 1. otherwise, a race may occur if jtag_trst_n is deasserted (going from low to high) on a rising edge of jtag _tck when jtag_tms is low, because the tap controller might go to either the run-test/idle state or stay in the test-logic-reset sta te. tsu_16b jtag_tck rising 2.4 ? ns thld_16b 1.0 ? ns jtag_tdo tdo_16c jtag_tck falling ? 20 ns tdz_16c 2 2. the values for this symbol were determined by calculation, not by testing. ?20ns jtag_trst_n tpw_16d 2 none 25.0 ? ns table 13 jtag ac timing characteristics tpw_16d tdz_16c tdo_16c thld_16b tsu_16b thld_16b tsu_16b tlow_16a tlow_16a tper_16a thigh_16a jtag_tck jtag_tdi jtag_tms jtag_tdo jtag_trst_n
23 of 54 november 28, 2011 idt 89HPES34H16G2 data sheet recommended operating supply voltages power-up/power-down sequence during power supply ramp-up, v dd core must remain at least 1.0v below v dd i/o at all times. there are no other power-up sequence require- ments for the various operating supply voltages. the power-down sequence can occur in any order. recommended operating temperature symbol parameter minimum typical maximum unit v dd core internal logic supply 0.9 1.0 1.1 v v dd i/o i/o supply except for serdes 2.25 2.5 2.75 v 3.125 3.3 3.465 v v dd pea 1 1. v dd pea and v dd peta should have no more than 25mv peak-peak ac power supply noise superimposed on the 1.0v nominal dc value. pci express analog power 0.95 1.0 1.1 v v dd peha 2 2. v dd peha should have no more than 50mv peak-peak ac power supply noise superimposed on the 2.5v nominal dc value. pci express analog high power 2.25 2.5 2.75 v v dd peta 1 pci express transmitter analog voltage 0.95 1.0 1.1 v v ss common ground 0 0 0 v table 14 pes34h16g2 operating voltages grade temperature commercial 0 c to +70 c ambient industrial -40 c to +85 c ambient table 15 pes34h16g2 operating temperatures
24 of 54 november 28, 2011 idt 89HPES34H16G2 data sheet power consumption typical power is measured under the following conditions: 25c ambient, 35% total link usage on all ports, typical voltages def ined in table 14 (and also listed below). maximum power is measured under the following conditions: 70c ambient, 85% total link usage on all ports, maximum voltages def ined in table 14 (and also listed below). note 1 : i/o supply of 3.3v is preferred. note 2 : the above power consumption assumes that all ports are f unctioning at gen2 (5.0 gt/s) speeds. power consumption can be reduced by turning off unused ports through software or through boot eeprom. power savings will occur in v dd pea, v dd peha, and v dd peta. power savings can be estimated as directly proportional to the number of unused ports, since the power consumption of a t urned- off port is close to zero. for example, if 3 ports out of 16 are turned off, then the power savings for each of the above three power rails can be calculated quite simply as 3/16 multiplied by t he power consumption indicated in the above table. note 3 : using a port in gen1 mode (2.5gt/s) results in appr oximately 18% power savings for each power rail: v dd pea, v dd peha, and v dd peta. number of active lanes per port core supply pcie digital supply pcie analog supply pcie transmitter supply i/o supply total typ 1.0v max 1.1v typ 1.0v max 1.1v typ 2.5v max 2.75v typ 1.0v max 1.1v typ 2.5v max 2.75v typ power max power three x8 and ten x1 (full swing) ma 3630 6264 1741 2049 805 818 1060 1117 32 40 watts 3.63 6.89 1.74 2.25 2.01 2.25 1.06 1.23 0.08 0.11 8.52 12.73 three x8 and ten x1 (half swing) ma 3630 6264 1497 1762 805 818 551 581 32 40 watts 3.63 6.89 1.50 1.94 2.01 2.25 0.55 0.64 0.08 0.11 7.77 11.83 table 16 pes34h16g2 power consumption ? 2.5v i/o number of active lanes per port core supply pcie digital supply pcie analog supply pcie transmitter supply i/o supply total typ 1.0v max 1.1v typ 1.0v max 1.1v typ 2.5v max 2.75v typ 1.0v max 1.1v typ 3.3v max 3.465v typ power max power three x8 and ten x1 (full swing) ma 3630 6264 1741 2049 805 818 1060 1117 36 46 watts 3.63 6.89 1.74 2.25 2.01 2.25 1.06 1.23 0.12 0.16 8.56 12.78 three x8 and ten x1 (half swing) ma 3630 6264 1497 1762 805 818 551 581 36 46 watts 3.63 6.89 1.50 1.94 2.01 2.25 0.55 0.64 0.12 0.16 7.81 11.88 table 17 pes34h16g2 power consumption ? 3.3v i/o
25 of 54 november 28, 2011 idt 89HPES34H16G2 data sheet thermal considerations this section describes thermal cons iderations for the pes34h16g2 (35x35 2 fcbga1156 package). the data in table 18 below contains informa- tion that is relevant to the thermal performance of the pes34h16g2 switch. note: it is important for the reliability of this device in any us er environment that the junction temperature not exceed the t j(max) value specified in table 18. consequently, the effectiv e junction to ambient thermal resistance ( ja ) for the worst case scenario must be maintained below the value determined by the formula: ja = (t j(max) - t a(max) )/p given that the values of t j(max) , t a(max) , and p are known, the value of desired ja becomes a known entity to the system designer. how to achieve the desired ja is left up to the board or system designer, but in general, it can be achieved by adding the effects of jc (value provided in table 18), thermal resistance of the chosen adhesive ( cs ), that of the heat sink ( sa ), amount of airflow, and properties of the circuit board (number of layers and size of the board). it is strongly recommended that users perform their own thermal analysi s for their own board and system design scenarios. symbol parameter value units conditions t j(max) junction temperature 125 o c maximum t a(max) ambient temperature 70 o c maximum for commercial-rated products 85 o c maximum for industrial-rated products ja(effective) effective thermal resistance, junction-to-ambient 13.0 o c/w zero air flow 6.8 o c/w 1 m/s air flow 5.8 o c/w 2 m/s air flow jb thermal resistance, junction-to-board 2.5 o c/w jc thermal resistance, junction-to-case 0.15 o c/w p power dissipation of the device 12.78 watts maximum table 18 thermal specifications for pes34h16g2, 35x35mm fcbga1156 package
26 of 54 november 28, 2011 idt 89HPES34H16G2 data sheet dc electrical characteristics values based on systems running at recommended supply voltages, as shown in table 14. note: see table 9, pin characteristics, for a complete i/o listing. i/o type parameter description gen1 gen2 unit condi- tions min 1 typ 1 max 1 min 1 typ 1 max 1 serial link pcie transmit v tx-diffp-p differential peak-to-peak output voltage 800 1200 800 1200 mv v tx-diffp-p-low low-drive differential peak to peak output voltage 400 1200 400 1200 mv v tx-de-ratio- 3.5db de-emphasized differential output voltage -3 -4 -3.0 -3.5 -4.0 db v tx-de-ratio- 6.0db de-emphasized differential output voltage na -5.5 -6.0 -6.5 db v tx-dc-cm dc common mode voltage 0 3.6 0 3.6 v v tx-cm-acp rms ac peak common mode output voltage 20 mv v tx-cm-dc-active- idle-delta abs delta of dc common mode voltage between l0 and idle 100 100 mv v tx-cm-dc-line- delta abs delta of dc common mode voltage between d+ and d- 25 25 mv v tx-idle-diffp electrical idle diff peak output 20 20 mv rl tx-diff transmitter differential return loss 10 10 db 0.05 - 1.25ghz 8 db 1.25 - 2.5ghz rl tx-cm transmitter common mode return loss 66db z tx-diff-dc dc differential tx impedance 80 100 120 120 vtx-cm-acpp peak-peak ac common na 100 mv v tx-dc-cm transmit driver dc common mode voltage 0 3.6 0 3.6 v v tx-rcv-detect the amount of voltage change allowed during receiver detec- tion 600 600 mv i tx-short transmitter short circuit current limit 090 90ma table 19 dc electrical characteristics (part 1 of 2)
27 of 54 november 28, 2011 idt 89HPES34H16G2 data sheet serial link (cont.) pcie receive v rx-diffp-p differential input voltage (peak-to- peak) 175 1200 120 1200 mv rl rx-diff receiver differential return loss 10 10 db 0.05 - 1.25ghz 8 1.25 - 2.5ghz rl rx-cm receiver common mode return loss 66db z rx-diff-dc differential input impedance (dc) 80 100 120 refer to return loss spec z rx--dc dc common mode impedance 40 50 60 40 60 z rx-comm-dc powered down input common mode impedance (dc) 200k 350k 50k z rx-high-imp-dc- pos dc input cm input impedance for v>0 during reset or power down 50k 50k z rx-high-imp-dc- neg dc input cm input impedance for v<0 during reset or power down 1.0k 1.0k v rx-idle-det- diffp-p electrical idle detect threshold 65 175 65 175 mv v rx-cm-acp receiver ac common-mode peak voltage 150 150 mv v rx-cm-acp pcie refclk c in input capacitance 1.5 ? 1.5 ? pf other i/os low drive output i ol ?2.5? ?2.5 ? mav ol = 0.4v i oh ?-5.5? ?-5.5 ? mav oh = 1.5v high drive output i ol ? 12.0 ? ? 12.0 ? ma v ol = 0.4v i oh ? -20.0 ? ? -20.0 ? ma v oh = 1.5v schmitt trig- ger input (sti) v il -0.3 ? 0.8 -0.3 ? 0.8 v ? v ih 2.0 ? v dd i/o + 0.5 2.0 ? v dd i/o + 0.5 v? input v il -0.3 ? 0.8 -0.3 ? 0.8 v ? v ih 2.0 ? v dd i/o + 0.5 2.0 ? v dd i/o + 0.5 v? capacitance c in ? ? 8.5 ? ? 8.5 pf ? leakage inputs ? ? + 10 ? ? + 10 av dd i/o (max) i/o leak w / o pull-ups/downs ??+ 10 ? ? + 10 av dd i/o (max) i/o leak with pull-ups/downs ??+ 80 ? ? + 80 av dd i/o (max) 1. minimum, typical, and maximum values meet the requirements under pci specification 2.0. i/o type parameter description gen1 gen2 unit condi- tions min 1 typ 1 max 1 min 1 typ 1 max 1 table 19 dc electrical characteristics (part 2 of 2)
28 of 54 november 28, 2011 idt 89HPES34H16G2 data sheet absolute maximum voltage rating warning: for proper and reliable operation in adherence with this data s heet, the device should not exceed the recommended operating vol tages in table 14. the absolute maximum operating voltages in table 20 are offered to provide guidelines for voltage excursions outsi de the recommended voltage ranges. device functionality is not guaranteed at these c onditions and sustained operation at these values or any expos ure to voltages outside the maximum range may adversely affect device functionality and reliability. smbus characterization core supply pcie analog supply pcie analog high supply pcie transmitter supply i/o supply 1.5v 1.5v 4.6v 1.5v 4.6v table 20 pes34h16g2 absolute maximum voltage rating symbol parameter smbus 2.0 char. data 1 1. data at room and hot temperature. unit 3v 3.3v 3.6v dc parameter for sda pin v il input low 1.16 1.26 1.35 v v ih input high 1.56 1.67 1.78 v v ol@350ua output low 15 15 15 mv i ol@0.4v 23 24 25 ma i pullup current source ? ? ? a i il_leak input low leakage 0 0 0 a i ih_leak input high leakage 0 0 0 a dc parameter for scl pin v il (v) input low 1.11 1.2 1.31 v v ih (v) input high 1.54 1.65 1.76 v i il_leak input low leakage 0 0 0 a i ih_leak input high leakage 0 0 0 a table 21 smbus dc characterization data
29 of 54 november 28, 2011 idt 89HPES34H16G2 data sheet symbol parameter smbus @3.3v 10% 1 1. data at room and hot temperature. unit min max f scl clock frequency 5 600 khz t buf bus free time between stop and start 3.5 ? s t hd:sta start condition hold time 1 ? s t su:sta start condition setup time 1 ? s t su:sto stop condition setup time 1 ? s t hd:dat data hold time 1 ? ns t su:dat data setup time 1 ? ns t timeout detect clock low time out ? 74.7 ms t low clock low period 3.7 ? s t high clock high period 3.7 ? s t f clock/data fall time ? 72.2 ns t r clock/data rise time ? 68.3 ns t por@10khz time which a device must be operational after power-on reset 20 ? ms table 22 smbus ac timing data
30 of 54 november 28, 2011 idt 89HPES34H16G2 data sheet package pinout ? 1156-bga signal pinout for the pes34h16g2 the following table lists the pin numbers and signal names for t he pes34h16g2 device. note: pins labeled nc are no connect. pin function alt pin function alt pin function alt pin function alt a1 v ss b1 v ss c1 gpio_29 2 d1 gpio_28 2 a2 v ss b2 v dd i/o c2 gpio_27 2 d2 gpio_26 2 a3 gpio_19 1 b3 gpio_18 1 c3 gpio_21 1 d3 v dd i/o a4 v dd i/o b4 gpio_17 1 c4 gpio_16 1 d4 gpio_23 2 a5 v ss b5 v ss c5 v ss d5 v ss a6 nc b6 nc c6 v ss d6 nc a7 nc b7 nc c7 v ss d7 nc a8 v ss b8 v ss c8 v ss d8 v ss a9 nc b9 nc c9 v ss d9 nc a10 pe09tp0 b10 pe09tn0 c10 v ss d10 pe09rn0 a11 v ss b11 v ss c11 v ss d11 v ss a12 nc b12 nc c12 v ss d12 nc a13 nc b13 nc c13 v ss d13 nc a14 v ss b14 v ss c14 v ss d14 v ss a15 nc b15 nc c15 v ss d15 nc a16 pe08tp0 b16 pe08tn0 c16 v ss d16 pe08rn0 a17 v ss b17 v ss c17 v ss d17 v ss a18 pe03tp3 b18 pe03tn3 c18 v ss d18 pe03rn3 a19 pe03tp2 b19 pe03tn2 c19 v ss d19 pe03rn2 a20 v ss b20 v ss c20 v ss d20 v ss a21 pe03tp1 b21 pe03tn1 c21 v ss d21 pe03rn1 a22 pe03tp0 b22 pe03tn0 c22 v ss d22 pe03rn0 a23 v ss b23 v ss c23 v ss d23 v ss a24 pe02tp3 b24 pe02tn3 c24 v ss d24 pe02rn3 a25 pe02tp2 b25 pe02tn2 c25 v ss d25 pe02rn2 a26 v ss b26 v ss c26 v ss d26 v ss a27 pe02tp1 b27 pe02tn1 c27 v ss d27 pe02rn1 a28 pe02tp0 b28 pe02tn0 c28 v ss d28 pe02rn0 a29 v ss b29 v ss c29 v ss d29 v ss a30 v dd i/o b30 msmbaddr3 c30 msmbaddr4 d30 jtag_tms a31 msmbaddr1 b31 msmbaddr2 c31 jtag_tdi d31 v dd i/o a32 msmbsmode b32 perstn c32 jtag_trst_n d32 ssmbaddr5 a33 v ss b33 v dd i/o c33 ssmbaddr2 d33 ssmbaddr3 a34 v ss b34 v ss c34 ssmbaddr1 d34 v dd i/o table 23 pes34h16g2 signal pin-out (part 1 of 9)
31 of 54 november 28, 2011 idt 89HPES34H16G2 data sheet e1 v dd i/o f1 v ss g1 pe10tp0 h1 nc e2 gpio_30 2 f2 v ss g2 pe10tn0 h2 nc e3 gpio_31 2 f3 v ss g3 v ss h3 v ss e4 gpio_24 2 f4 v ss g4 pe10rn0 h4 nc e5 v ss f5 v ss g5 pe10rp0 h5 nc e6 nc f6 v ss g6 v ss h6 v ss e7 nc f7 v ss g7 v ss h7 v ss e8 v ss f8 v ss g8 v ss h8 gpio_20 1 e9 nc f9 v ss g9 v ss h9 v dd i/o e10 pe09rp0 f10 refres09 g10 v ss h10 v ss e11 v ss f11 v ss g11 v ss h11 v ss e12 nc f12 v ss g12 nc h12 v ss e13 nc f13 v ss g13 v ss h13 v dd peha e14 v ss f14 v ss g14 v ss h14 v ss e15 nc f15 v ss g15 nc h15 v dd peta e16 pe08rp0 f16 v ss g16 v ss h16 v ss e17 v ss f17 refrespll g17 gclkn0 h17 v ss e18 pe03rp3 f18 v ss g18 gclkp0 h18 v ss e19 pe03rp2 f19 refres03 g19 nc h19 v ss e20 v ss f20 v ss g20 v ss h20 v dd peta e21 pe03rp1 f21 v ss g21 v ss h21 refres02 e22 pe03rp0 f22 v ss g22 nc h22 v dd peha e23 v ss f23 v ss g23 v ss h23 v ss e24 pe02rp3 f24 v ss g24 v ss h24 v ss e25 pe02rp2 f25 v ss g25 v ss h25 v ss e26 v ss f26 v ss g26 v ss h26 msmbdat e27 pe02rp1 f27 v ss g27 msmbclk h27 v dd i/o e28 pe02rp0 f28 v ss g28 v ss h28 ssmbclk e29 v ss f29 v ss g29 v ss h29 v ss e30 v ss f30 pe01rp3 g30 pe01rp2 h30 v ss e31 v ss f31 pe01rn3 g31 pe01rn2 h31 v ss e32 v ss f32 v ss g32 v ss h32 v ss e33 v ss f33 pe01tn3 g33 pe01tn2 h33 v ss e34 v ss f34 pe01tp3 g34 pe01tp2 h34 v ss pin function alt pin function alt pin function alt pin function alt table 23 pes34h16g2 signal pin-out (part 2 of 9)
32 of 54 november 28, 2011 idt 89HPES34H16G2 data sheet j1 v ss k1 nc l1 nc m1 v ss j2 v ss k2 nc l2 nc m2 v ss j3 v ss k3 v ss l3 v ss m3 v ss j4 v ss k4 nc l4 nc m4 v ss j5 v ss k5 nc l5 nc m5 v ss j6 v ss k6 v ss l6 v ss m6 v ss j7 v ss k7 v ss l7 v ss m7 v ss j8 v ss k8 v ss l8 v ss m8 v ss j9 gpio_25 2 k9 v dd i/o l9 v ss m9 v ss j10 v ss k10 gpio_22 2 l10 v ss m10 v ss j11 v ss k11 v ss l11 v ss m11 v ss j12 v ss k12 v ss l12 v ss m12 v ss j13 v ss k13 v dd peha l13 v dd pea m13 v dd pea j14 v dd pea k14 v ss l14 v dd pea m14 v ss j15 refres08 k15 v dd peta l15 v dd pea m15 v dd pea j16 v ss k16 v ss l16 v ss m16 v ss j17 v dd peha k17 v dd peha l17 v dd pea m17 v dd pea j18 v dd peha k18 v dd peha l18 v dd pea m18 v dd pea j19 v ss k19 v ss l19 v ss m19 v ss j20 v ss k20 v dd peta l20 v dd pea m20 v dd pea j21 v dd pea k21 v ss l21 v dd pea m21 v ss j22 v ss k22 v dd peha l22 v dd pea m22 v dd pea j23 v ss k23 v ss l23 v ss m23 v ss j24 v ss k24 v ss l24 v ss m24 v ss j25 jtag_tdo k25 clkmode1 l25 v ss m25 v ss j26 v dd i/o k26 jtag_tck l26 v ss m26 v ss j27 ssmbdat k27 v ss l27 v ss m27 v ss j28 v ss k28 v ss l28 v ss m28 refres01 j29 v ss k29 v ss l29 v ss m29 v ss j30 pe01rp1 k30 pe01rp0 l30 v ss m30 pe00rp3 j31 pe01rn1 k31 pe01rn0 l31 v ss m31 pe00rn3 j32 v ss k32 v ss l32 v ss m32 v ss j33 pe01tn1 k33 pe01tn0 l33 v ss m33 pe00tn3 j34 pe01tp1 k34 pe01tp0 l34 v ss m34 pe00tp3 pin function alt pin function alt pin function alt pin function alt table 23 pes34h16g2 signal pin-out (part 3 of 9)
33 of 54 november 28, 2011 idt 89HPES34H16G2 data sheet n1 pe11tp0 p1 nc r1 v ss t1 nc n2 pe11tn0 p2 nc r2 v ss t2 nc n3 v ss p3 v ss r3 v ss t3 v ss n4 pe11rn0 p4 nc r4 v ss t4 nc n5 pe11rp0 p5 nc r5 v ss t5 nc n6 v ss p6 v ss r6 v ss t6 nc n7 nc p7 v ss r7 refres10 t7 v ss n8 v dd peha p8 v ss r8 v dd peta t8 v ss n9 v ss p9 v dd pea r9 v ss t9 refres11 n10 v dd peha p10 v ss r10 v dd peta t10 v ss n11 v dd pea p11 v dd pea r11 v dd pea t11 v ss n12 v dd pea p12 v ss r12 v dd pea t12 v ss n13 v dd core p13 v dd core r13 v dd core t13 v ss n14 v dd core p14 v ss r14 v dd core t14 v ss n15 v dd core p15 v dd core r15 v ss t15 v dd core n16 v ss p16 v ss r16 v dd core t16 v ss n17 v dd core p17 v dd core r17 v ss t17 v dd core n18 v ss p18 v ss r18 v dd core t18 v ss n19 v dd core p19 v dd core r19 v ss t19 v dd core n20 v dd core p20 v ss r20 v dd core t20 v ss n21 v dd core p21 v dd core r21 v ss t21 v dd core n22 v dd core p22 v dd core r22 v dd core t22 v dd core n23 v dd pea p23 v ss r23 v dd pea t23 v ss n24 v dd pea p24 v dd pea r24 v dd pea t24 v ss n25 v dd peha p25 v ss r25 v dd peta t25 v ss n26 v ss p26 v dd pea r26 v ss t26 v ss n27 v dd peha p27 v ss r27 v dd peta t27 v ss n28 nc p28 v ss r28 v ss t28 v ss n29 v ss p29 v ss r29 refres00 t29 nc n30 pe00rp2 p30 v ss r30 pe00rp1 t30 pe00rp0 n31 pe00rn2 p31 v ss r31 pe00rn1 t31 pe00rn0 n32 v ss p32 v ss r32 v ss t32 v ss n33 pe00tn2 p33 v ss r33 pe00tn1 t33 pe00tn0 n34 pe00tp2 p34 v ss r34 pe00tp1 t34 pe00tp0 pin function alt pin function alt pin function alt pin function alt table 23 pes34h16g2 signal pin-out (part 4 of 9)
34 of 54 november 28, 2011 idt 89HPES34H16G2 data sheet u1 nc v1 v ss w1 pe04tp0 y1 pe04tp1 u2 nc v2 v ss w2 pe04tn0 y2 pe04tn1 u3 v ss v3 v ss w3 v ss y3 v ss u4 nc v4 v ss w4 pe04rn0 y4 pe04rn1 u5 nc v5 v ss w5 pe04rp0 y5 pe04rp1 u6 v ss v6 v ss w6 v ss y6 nc u7 nc v7 nc w7 v ss y7 refres04 u8 v ss v8 v ss w8 v ss y8 v dd peta u9 v dd peha v9 v dd peha w9 v ss y9 v ss u10 v dd peha v10 v dd peha w10 v ss y10 v dd peta u11 v dd pea v11 v dd pea w11 v ss y11 v dd pea u12 v dd pea v12 v dd pea w12 v ss y12 v dd pea u13 v dd core v13 v ss w13 v dd core y13 v dd core u14 v dd core v14 v ss w14 v dd core y14 v ss u15 v ss v15 v dd core w15 v ss y15 v dd core u16 v dd core v16 v ss w16 v dd core y16 v ss u17 v ss v17 v dd core w17 v ss y17 v dd core u18 v dd core v18 v ss w18 v dd core y18 v ss u19 v ss v19 v dd core w19 v ss y19 v dd core u20 v dd core v20 v ss w20 v dd core y20 v ss u21 v ss v21 v dd core w21 v ss y21 v dd core u22 v ss v22 v dd core w22 v ss y22 v dd core u23 v dd pea v23 v dd pea w23 v ss y23 v dd pea u24 v dd pea v24 v dd pea w24 v ss y24 v dd pea u25 v dd peha v25 v dd peha w25 v ss y25 v dd peta u26 v dd peha v26 v dd peha w26 nc y26 v ss u27 v ss v27 v ss w27 v ss y27 v dd peta u28 nc v28 nc w28 v ss y28 v ss u29 v ss v29 v ss w29 refres15 y29 nc u30 v ss v30 nc w30 nc y30 v ss u31 v ss v31 nc w31 nc y31 v ss u32 v ss v32 v ss w32 v ss y32 v ss u33 v ss v33 nc w33 nc y33 v ss u34 v ss v34 nc w34 nc y34 v ss pin function alt pin function alt pin function alt pin function alt table 23 pes34h16g2 signal pin-out (part 5 of 9)
35 of 54 november 28, 2011 idt 89HPES34H16G2 data sheet aa1 v ss ab1 pe04tp2 ac1 pe04tp3 ad1 v ss aa2 v ss ab2 pe04tn2 ac2 pe04tn3 ad2 v ss aa3 v ss ab3 v ss ac3 v ss ad3 v ss aa4 v ss ab4 pe04rn2 ac4 pe04rn3 ad4 v ss aa5 v ss ab5 pe04rp2 ac5 pe04rp3 ad5 v ss aa6 v ss ab6 refres05 ac6 v ss ad6 v ss aa7 v ss ab7 nc ac7 v ss ad7 v ss aa8 v ss ab8 v dd peha ac8 v ss ad8 v ss aa9 v dd pea ab9 v ss ac9 v ss ad9 nc aa10 v ss ab10 v dd peha ac10 v ss ad10 nc aa11 v dd pea ab11 v dd pea ac11 v ss ad11 v ss aa12 v ss ab12 v dd pea ac12 v ss ad12 v ss aa13 v dd core ab13 v dd core ac13 v dd pea ad13 v dd pea aa14 v dd core ab14 v dd core ac14 v ss ad14 v dd pea aa15 v ss ab15 v dd core ac15 v dd pea ad15 v dd pea aa16 v dd core ab16 v dd core ac16 v ss ad16 v ss aa17 v ss ab17 v ss ac17 v dd pea ad17 v dd pea aa18 v dd core ab18 v dd core ac18 v dd pea ad18 v dd pea aa19 v ss ab19 v ss ac19 v ss ad19 v ss aa20 v dd core ab20 v dd core ac20 v dd pea ad20 v dd pea aa21 v ss ab21 v dd core ac21 v ss ad21 v dd pea aa22 v dd core ab22 v dd core ac22 v dd pea ad22 v dd pea aa23 v ss ab23 v dd pea ac23 v ss ad23 v ss aa24 v dd pea ab24 v dd pea ac24 v ss ad24 v ss aa25 v ss ab25 v dd peha ac25 v ss ad25 v ss aa26 v dd pea ab26 v ss ac26 v ss ad26 v ss aa27 v ss ab27 v dd peha ac27 v ss ad27 v ss aa28 v ss ab28 v ss ac28 v ss ad28 v ss aa29 refres14 ab29 v ss ac29 v ss ad29 v ss aa30 nc ab30 pe15rp0 ac30 v ss ad30 nc aa31 nc ab31 pe15rn0 ac31 v ss ad31 nc aa32 v ss ab32 v ss ac32 v ss ad32 v ss aa33 nc ab33 pe15tn0 ac33 v ss ad33 nc aa34 nc ab34 pe15tp0 ac34 v ss ad34 nc pin function alt pin function alt pin function alt pin function alt table 23 pes34h16g2 signal pin-out (part 6 of 9)
36 of 54 november 28, 2011 idt 89HPES34H16G2 data sheet ae1 pe05tp0 af1 pe05tp1 ag1 v ss ah1 pe05tp2 ae2 pe05tn0 af2 pe05tn1 ag2 v ss ah2 pe05tn2 ae3 v ss af3 v ss ag3 v ss ah3 v ss ae4 pe05rn0 af4 pe05rn1 ag4 v ss ah4 pe05rn2 ae5 pe05rp0 af5 pe05rp1 ag5 v ss ah5 pe05rp2 ae6 v ss af6 v ss ag6 v ss ah6 v ss ae7 v ss af7 v ss ag7 clkmode0 ah7 v ss ae8 v ss af8 v ss ag8 v dd i/o ah8 gclkfsel ae9 v dd i/o af9 v dd i/o ag9 v ss ah9 v ss ae10 v ss af10 v dd i/o ag10 v ss ah10 v ss ae11 v ss af11 v ss ag11 v ss ah11 v ss ae12 v ss af12 v ss ag12 v ss ah12 v ss ae13 v dd peha af13 v ss ag13 v dd peha ah13 v ss ae14 v ss af14 v dd pea ag14 v ss ah14 refres06 ae15 v dd peta af15 v ss ag15 v dd peta ah15 v ss ae16 v ss af16 v ss ag16 v ss ah16 nc ae17 v dd peha af17 v dd peha ag17 v ss ah17 gclkp1 ae18 v dd peha af18 v dd peha ag18 v ss ah18 gclkn1 ae19 v ss af19 v ss ag19 v ss ah19 v ss ae20 v dd peta af20 v ss ag20 v dd peta ah20 refres12 ae21 v ss af21 v dd pea ag21 nc ah21 v ss ae22 v dd peha af22 v ss ag22 v dd peha ah22 nc ae23 v ss af23 v ss ag23 v ss ah23 refres13 ae24 v ss af24 v ss ag24 v ss ah24 v ss ae25 gpio_06 af25 v ss ag25 v ss ah25 v ss ae26 v dd i/o af26 gpio_09 1 ag26 v dd i/o ah26 v ss ae27 v ss af27 v ss ag27 gpio_04 1 ah27 v ss ae28 v ss af28 v ss ag28 v ss ah28 v ss ae29 v ss af29 v ss ag29 v ss ah29 v ss ae30 nc af30 v ss ag30 nc ah30 pe14rp0 ae31 nc af31 v ss ag31 nc ah31 pe14rn0 ae32 v ss af32 v ss ag32 v ss ah32 v ss ae33 nc af33 v ss ag33 nc ah33 pe14tn0 ae34 nc af34 v ss ag34 nc ah34 pe14tp0 pin function alt pin function alt pin function alt pin function alt table 23 pes34h16g2 signal pin-out (part 7 of 9)
37 of 54 november 28, 2011 idt 89HPES34H16G2 data sheet aj1 pe05tp3 ak1 v ss al1 v dd i/o am1 p23mergen aj2 pe05tn3 ak2 v ss al2 p01mergen am2 v dd i/o aj3 v ss ak3 v ss al3 p45mergen am3 v dd i/o aj4 pe05rn3 ak4 v ss al4 v dd i/o am4 v dd i/o aj5 pe05rp3 ak5 v ss al5 v dd i/o am5 swmode3 aj6 v ss ak6 v ss al6 v ss am6 v ss aj7 v ss ak7 pe06rp0 al7 pe06rn0 am7 v ss aj8 v ss ak8 nc al8 nc am8 v ss aj9 v ss ak9 v ss al9 v ss am9 v ss aj10 v ss ak10 nc al10 nc am10 v ss aj11 v ss ak11 nc al11 nc am11 v ss aj12 v ss ak12 v ss al12 v ss am12 v ss aj13 v ss ak13 pe07rp0 al13 pe07rn0 am13 v ss aj14 nc ak14 nc al14 nc am14 v ss aj15 v ss ak15 v ss al15 v ss am15 v ss aj16 refres07 ak16 nc al16 nc am16 v ss aj17 v ss ak17 nc al17 nc am17 v ss aj18 v ss ak18 v ss al18 v ss am18 v ss aj19 v ss ak19 pe12rp0 al19 pe12rn0 am19 v ss aj20 v ss ak20 nc al20 nc am20 v ss aj21 v ss ak21 v ss al21 v ss am21 v ss aj22 v ss ak22 nc al22 nc am22 v ss aj23 v ss ak23 nc al23 nc am23 v ss aj24 v ss ak24 v ss al24 v ss am24 v ss aj25 v ss ak25 pe13rp0 al25 pe13rn0 am25 v ss aj26 v ss ak26 nc al26 nc am26 v ss aj27 v ss ak27 v ss al27 v ss am27 v ss aj28 v ss ak28 nc al28 nc am28 v ss aj29 v ss ak29 nc al29 nc am29 v ss aj30 v ss ak30 v ss al30 v ss am30 v ss aj31 v ss ak31 gpio_08 1 al31 gpio_07 am31 gpio_00 1 aj32 v ss ak32 gpio_15 1 al32 v dd i/o am32 gpio_05 2 aj33 v ss ak33 gpio_14 1 al33 gpio_10 1 am33 gpio_11 1 aj34 v ss ak34 v dd i/o al34 gpio_12 1 am34 gpio_13 1 pin function alt pin function alt pin function alt pin function alt table 23 pes34h16g2 signal pin-out (part 8 of 9)
38 of 54 november 28, 2011 idt 89HPES34H16G2 data sheet alternate signal functions an1 v ss an18 v ss ap1 v ss ap18 v ss an2 v dd i/o an19 pe12tn0 ap2 v ss ap19 pe12tp0 an3 v dd i/o an20 nc ap3 rsthalt ap20 nc an4 swmode0 an21 v ss ap4 swmode1 ap21 v ss an5 swmode2 an22 nc ap5 v dd i/o ap22 nc an6 v ss an23 nc ap6 v ss ap23 nc an7 pe06tn0 an24 v ss ap7 pe06tp0 ap24 v ss an8 nc an25 pe13tn0 ap8 nc ap25 pe13tp0 an9 v ss an26 nc ap9 v ss ap26 nc an10 nc an27 v ss ap10 nc ap27 v ss an11 nc an28 nc ap11 nc ap28 nc an12 v ss an29 nc ap12 v ss ap29 nc an13 pe07tn0 an30 v ss ap13 pe07tp0 ap30 v ss an14 nc an31 gpio_01 1 ap14 nc ap31 v dd i/o an15 v ss an32 gpio_02 1 ap15 v ss ap32 gpio_03 1 an16 nc an33 v dd i/o ap16 nc ap33 v ss an17 nc an34 v ss ap17 nc ap34 v ss pin gpio 1st alternate 2nd alternate pin gpio 1st alternate 2nd alternate am31 gpio_00 part0perstn ? b4 gpio_17 hp0rstn ? an31 gpio_01 part1perstn ? b3 gpio_18 hp1apn ? an32 gpio_02 part2perstn ? a3 gpio_19 hp1pdn ? ap32 gpio_03 part3perstn h8 gpio_20 hp1pfn ? ag27 gpio_04 ? p0linkupn c3 gpio_21 hp1pwrgdn ? am32 gpio_05 gpen p0activen k10 gpio_22 hp1mrln p1linkupn ak31 gpio_08 ioexpintn ? d4 gpio_23 hp1ain p1activen af26 gpio_09 hp0apn ? e4 gpio_24 hp1pin p2linkupn al33 gpio_10 hp0pdn ? j9 gpio_25 hp1pep p2activen am33 gpio_11 hp0pfn ? d2 gpio_26 hp1rstn p3linkupn al34 gpio_12 hp0pwrgdn ? c2 gpio_27 hp2apn p3activen am34 gpio_13 hp0mrln ? d1 gpio_28 hp2pdn p4linkupn ak33 gpio_14 hp0ain ? c1 gpio_29 hp2pfn p4activen ak32 gpio_15 hp0pin ? e2 gpio_30 hp2pwrgdn p5linkupn c4 gpio_16 hp0pep ? e3 gpio_31 hp2mrln p5activen table 24 pes34h16g2 alternate signal functions pin function alt pin function alt pin function alt pin function alt table 23 pes34h16g2 signal pin-out (part 9 of 9)
39 of 54 november 28, 2011 idt 89HPES34H16G2 data sheet power pins v dd core v dd core v dd i/o v dd pea v dd pea v dd peha v dd peta n13 v15 a4 j14 v11 h13 h15 n14 v17 a30 j21 v12 h22 h20 n15 v19 b2 l13 v23 j17 k15 n17 v21 b33 l14 v24 j18 k20 n19 v22 d3 l15 y11 k13 r8 n20 w13 d31 l17 y12 k17 r10 n21 w14 d34 l18 y23 k18 r25 n22 w16 e1 l20 y24 k22 r27 p13 w18 h9 l21 aa9 n8 y8 p15 w20 h27 l22 aa11 n10 y10 p17 y13 j26 m13 aa24 n25 y25 p19 y15 k9 m15 aa26 n27 y27 p21 y17 ae9 m17 ab11 u9 ae15 p22 y19 ae26 m18 ab12 u10 ae20 r13 y21 af9 m20 ab23 u25 ag15 r14 y22 af10 m22 ab24 u26 ag20 r16 aa13 ag8 n11 ac13 v9 r18 aa14 ag26 n12 ac15 v10 r20 aa16 ak34 n23 ac17 v25 r22aa18al1 n24ac18v26 t15 aa20 al4 p9 ac20 ab8 t17 aa22 al5 p11 ac22 ab10 t19 ab13 al32 p24 ad13 ab25 t21 ab14 am2 p26 ad14 ab27 t22 ab15 am3 r11 ad15 ae13 u13 ab16 am4 r12 ad17 ae17 u14 ab18 an2 r23 ad18 ae18 u16 ab20 an3 r24 ad20 ae22 u18 ab21 an33 u11 ad21 af17 u20 ab22 ap5 u12 ad22 af18 ap31 u23 af14 ag13 u24 af21 ag22 table 25 pes34h16g2 power pins
40 of 54 november 28, 2011 idt 89HPES34H16G2 data sheet ground pins v ss v ss v ss v ss v ss v ss v ss v ss a1 c16 e33 g11 j3 l3 m16 p32 a2 c17 e34 g13 j4 l6 m19 p33 a5 c18 f1 g14 j5 l7 m21 p34 a8 c19 f2 g16 j6 l8 m23 r1 a11 c20 f3 g20 j7 l9 m24 r2 a14 c21 f4 g21 j8 l10 m25 r3 a17 c22 f5 g23 j10 l11 m26 r4 a20 c23 f6 g24 j11 l12 m27 r5 a23 c24 f7 g25 j12 l16 m29 r6 a26 c25 f8 g26 j13 l19 m32 r9 a29 c26 f9 g28 j16 l23 n3 r15 a33 c27 f11 g29 j19 l24 n6 r17 a34 c28 f12 g32 j20 l25 n9 r19 b1 c29 f13 h3 j22 l26 n16 r21 b5 d5 f14 h6 j23 l27 n18 r26 b8 d8 f15 h7 j24 l28 n26 r28 b11 d11 f16 h10 j28 l29 n29 r32 b14 d14 f18 h11 j29 l30 n32 t3 b17 d17 f20 h12 j32 l31 p3 t7 b20 d20 f21 h14 k3 l32 p6 t8 b23 d23 f22 h16 k6 l33 p7 t10 b26 d26 f23 h17 k7 l34 p8 t11 b29 d29 f24 h18 k8 m1 p10 t12 b34 e5 f25 h19 k11 m2 p12 t13 c5 e8 f26 h23 k12 m3 p14 t14 c6 e11 f27 h24 k14 m4 p16 t16 c7 e14 f28 h25 k16 m5 p18 t18 c8 e17 f29 h29 k19 m6 p20 t20 c9 e20 f32 h30 k21 m7 p23 t23 c10 e23 g3 h31 k23 m8 p25 t24 c11 e26 g6 h32 k24 m9 p27 t25 c12 e29 g7 h33 k27 m10 p28 t26 c13 e30 g8 h34 k28 m11 p29 t27 c14 e31 g9 j1 k29 m12 p30 t28 c15 e32 g10 j2 k32 m14 p31 t32 table 26 pes34h16g2 ground pins (part 1 of 3)
41 of 54 november 28, 2011 idt 89HPES34H16G2 data sheet u3 w12 aa19 ac33 ae29 ag17 aj17 al21 u6 w15 aa21 ac34 ae32 ag18 aj18 al24 u8 w17 aa23 ad1 af3 ag19 aj19 al27 u15 w19 aa25 ad2 af6 ag23 aj20 al30 u17 w21 aa27 ad3 af7 ag24 aj21 am6 u19 w22 aa28 ad4 af8 ag25 aj22 am7 u21 w23 aa32 ad5 af11 ag28 aj23 am8 u22 w24 ab3 ad6 af12 ag29 aj24 am9 u27 w25 ab9 ad7 af13 ag32 aj25 am10 u29 w27 ab17 ad8 af15 ah3 aj26 am11 u30 w28 ab19 ad11 af16 ah6 aj27 am12 u31 w32 ab26 ad12 af19 ah7 aj28 am13 u32 y3 ab28 ad16 af20 ah9 aj29 am14 u33 y9 ab29 ad19 af22 ah10 aj30 am15 u34 y14 ab32 ad23 af23 ah11 aj31 am16 v1 y16 ac3 ad24 af24 ah12 aj32 am17 v2 y18 ac6 ad25 af25 ah13 aj33 am18 v3 y20 ac7 ad26 af27 ah15 aj34 am19 v4 y26 ac8 ad27 af28 ah19 ak1 am20 v5 y28 ac9 ad28 af29 ah21 ak2 am21 v6 y30 ac10 ad29 af30 ah24 ak3 am22 v8 y31 ac11 ad32 af31 ah25 ak4 am23 v13 y32 ac12 ae3 af32 ah26 ak5 am24 v14 y33 ac14 ae6 af33 ah27 ak6 am25 v16 y34 ac16 ae7 af34 ah28 ak9 am26 v18 aa1 ac19 ae8 ag1 ah29 ak12 am27 v20 aa2 ac21 ae10 ag2 ah32 ak15 am28 v27 aa3 ac23 ae11 ag3 aj3 ak18 am29 v29 aa4 ac24 ae12 ag4 aj6 ak21 am30 v32 aa5 ac25 ae14 ag5 aj7 ak24 an1 w3 aa6 ac26 ae16 ag6 aj8 ak27 an6 w6 aa7 ac27 ae19 ag9 aj9 ak30 an9 w7 aa8 ac28 ae21 ag10 aj10 al6 an12 w8 aa10 ac29 ae23 ag11 aj11 al9 an15 w9 aa12 ac30 ae24 ag12 aj12 al12 an18 w10 aa15 ac31 ae27 ag14 aj13 al15 an21 w11 aa17 ac32 ae28 ag16 aj15 al18 an24 v ss v ss v ss v ss v ss v ss v ss v ss table 26 pes34h16g2 ground pins (part 2 of 3)
42 of 54 november 28, 2011 idt 89HPES34H16G2 data sheet no connection pins an27 an34 ap2 ap9 ap15 ap21 ap27 ap33 an30 ap1 ap6 ap12 ap18 ap24 ap30 ap34 nc nc nc nc nc nc a6 g12 t4 aa31 ak11 an11 a7 g15 t5 aa33 ak14 an14 a9 g19 t6 aa34 ak16 an16 a12 g22 t29 ab7 ak17 an17 a13 h1 u1 ad9 ak20 an20 a15 h2 u2 ad10 ak22 an22 b6 h4 u4 ad30 ak23 an23 b7 h5 u5 ad31 ak26 an26 b9 k1 u7 ad33 ak28 an28 b12 k2 u28 ad34 ak29 an29 b13 k4 v7 ae30 al8 ap8 b15 k5 v28 ae31 al10 ap10 d6 l1 v30 ae33 al11 ap11 d7 l2 v31 ae34 al14 ap14 d9 l4 v33 ag21 al16 ap16 d12 l5 v34 ag30 al17 ap17 d13 n7 w26 ag31 al20 ap20 d15 n28 w30 ag33 al22 ap22 e6 p1 w31 ag34 al23 ap23 e7 p2 w33 ah16 al26 ap26 e9 p4 w34 ah22 al28 ap28 e12 p5 y6 aj14 al29 ap29 e13 t1 y29 ak8 an8 e15 t2 aa30 ak10 an10 table 27 pes34h16g2 no connection pins v ss v ss v ss v ss v ss v ss v ss v ss table 26 pes34h16g2 ground pins (part 3 of 3)
43 of 54 november 28, 2011 idt 89HPES34H16G2 data sheet signals listed alphabetically signal name i/o type location signal category clkmode0 i ag7 system clkmode1 i k25 gclkfsel i ah8 gclkn0 i g17 gclkn1 i ah18 gclkp0 i g18 gclkp1 i ah17 gpio_00 i/o am31 general purpose i/o gpio_01 i/o an31 gpio_02 i/o an32 gpio_03 i/o ap32 gpio_04 i/o ag27 gpio_05 i/o am32 gpio_06 i/o ae25 gpio_07 i/o al31 gpio_08 i/o ak31 gpio_09 i/o af26 gpio_10 i/o al33 gpio_11 i/o am33 gpio_12 i/o al34 gpio_13 i/o am34 gpio_14 i/o ak33 gpio_15 i/o ak32 gpio_16 i/o c4 gpio_17 i/o b4 gpio_18 i/o b3 gpio_19 i/o a3 gpio_20 i/o h8 gpio_21 i/o c3 gpio_22 i/o k10 gpio_23 i/o d4 gpio_24 i/o e4 gpio_25 i/o j9 gpio_26 i/o d2 table 28 pes34h16g2 alphabetical signal list (part 1 of 7)
44 of 54 november 28, 2011 idt 89HPES34H16G2 data sheet gpio_27 i/o c2 general purpose i/o (cont.) gpio_28 i/o d1 gpio_29 i/o c1 gpio_30 i/o e2 gpio_31 i/o e3 jtag_tck i k26 test jtag_tdi i c31 jtag_tdo o j25 jtag_tms i d30 jtag_trst_n i c32 msmbaddr1 i a31 smbus interface msmbaddr2 i b31 msmbaddr3 i b30 msmbaddr4 i c30 msmbclk i/o g27 msmbdat i/o h26 msmbsmode i a32 system no connection see table 27 for a listing of no connect pins. p01mergen i al2 system p23mergen i am1 p45mergen i al3 pe00rn0 i t31 pci express pe00rn1 i r31 pe00rn2 i n31 pe00rn3 i m31 pe00rp0 i t30 pe00rp1 i r30 pe00rp2 i n30 pe00rp3 i m30 pe00tn0 o t33 pe00tn1 o r33 pe00tn2 o n33 pe00tn3 o m33 pe00tp0 o t34 pe00tp1 o r34 pe00tp2 o n34 signal name i/o type location signal category table 28 pes34h16g2 alphabetical signal list (part 2 of 7)
45 of 54 november 28, 2011 idt 89HPES34H16G2 data sheet pe00tp3 o m34 pci express (cont.) pe01rn0 i k31 pe01rn1 i j31 pe01rn2 i g31 pe01rn3 i f31 pe01rp0 i k30 pe01rp1 i j30 pe01rp2 i g30 pe01rp3 i f30 pe01tn0 o k33 pe01tn1 o j33 pe01tn2 o g33 pe01tn3 o f33 pe01tp0 o k34 pe01tp1 o j34 pe01tp2 o g34 pe01tp3 o f34 pe02rn0 i d28 pe02rn1 i d27 pe02rn2 i d25 pe02rn3 i d24 pe02rp0 i e28 pe02rp1 i e27 pe02rp2 i e25 pe02rp3 i e24 pe02tn0 o b28 pe02tn1 o b27 pe02tn2 o b25 pe02tn3 o b24 pe02tp0 o a28 pe02tp1 o a27 pe02tp2 o a25 pe02tp3 o a24 pe03rn0 i d22 pe03rn1 i d21 pe03rn2 i d19 signal name i/o type location signal category table 28 pes34h16g2 alphabetical signal list (part 3 of 7)
46 of 54 november 28, 2011 idt 89HPES34H16G2 data sheet pe03rn3 i d18 pci express (cont.) pe03rp0 i e22 pe03rp1 i e21 pe03rp2 i e19 pe03rp3 i e18 pe03tn0 o b22 pe03tn1 o b21 pe03tn2 o b19 pe03tn3 o b18 pe03tp0 o a22 pe03tp1 o a21 pe03tp2 o a19 pe03tp3 o a18 pe04rn0 i w4 pe04rn1 i y4 pe04rn2 i ab4 pe04rn3 i ac4 pe04rp0 i w5 pe04rp1 i y5 pe04rp2 i ab5 pe04rp3 i ac5 pe04tn0 o w2 pe04tn1 o y2 pe04tn2 o ab2 pe04tn3 o ac2 pe04tp0 o w1 pe04tp1 o y1 pe04tp2 o ab1 pe04tp3 o ac1 pe05rn0 i ae4 pe05rn1 i af4 pe05rn2 i ah4 pe05rn3 i aj4 pe05rp0 i ae5 pe05rp1 i af5 pe05rp2 i ah5 signal name i/o type location signal category table 28 pes34h16g2 alphabetical signal list (part 4 of 7)
47 of 54 november 28, 2011 idt 89HPES34H16G2 data sheet pe05rp3 i aj5 pci express (cont.) pe05tn0 o ae2 pe05tn1 o af2 pe05tn2 o ah2 pe05tn3 o aj2 pe05tp0 o ae1 pe05tp1 o af1 pe05tp2 o ah1 pe05tp3 o aj1 pe06rn0 i al7 pe06rp0 i ak7 pe06tn0 o an7 pe06tp0 o ap7 pe07rn0 i al13 pe07rp0 i ak13 pe07tn0 o an13 pe07tp0 o ap13 pe08rn0 i d16 pe08rp0 i e16 pe08tn0 o b16 pe08tp0 o a16 pe09rn0 i d10 pe09rp0 i e10 pe09tn0 o b10 pe09tp0 o a10 pe10rn0 i g4 pe10rp0 i g5 pe10tn0 o g2 pe10tp0 o g1 pe11rn0 i n4 pe11rp0 i n5 pe11tn0 o n2 pe11tp0 o n1 pe12rn0 i al19 pe12rp0 i ak19 pe12tn0 o an19 signal name i/o type location signal category table 28 pes34h16g2 alphabetical signal list (part 5 of 7)
48 of 54 november 28, 2011 idt 89HPES34H16G2 data sheet pe12tp0 o ap19 pci express (cont.) pe13rn0 i al25 pe13rp0 i ak25 pe13tn0 o an25 pe13tp0 o ap25 pe14rn0 i ah31 pe14rp0 i ah30 pe14tn0 o ah33 pe14tp0 o ah34 pe15rn0 i ab31 pe15rp0 i ab30 pe15tn0 o ab33 pe15tp0 o ab34 perstn i b32 system refres00 i/o r29 serdes reference resistors refres01 i/o m28 refres02 i/o h21 refres03 i/o f19 refres04 i/o y7 refres05 i/o ab6 refres06 i/o ah14 refres07 i/o aj16 refres08 i/o j15 refres09 i/o f10 refres10 i/o r7 refres11 i/o t9 refres12 i/o ah20 refres13 i/o ah23 refres14 i/o aa29 refres15 i/o w29 refrespll i/o f17 rsthalt i ap3 system signal name i/o type location signal category table 28 pes34h16g2 alphabetical signal list (part 6 of 7)
49 of 54 november 28, 2011 idt 89HPES34H16G2 data sheet ssmbaddr1 i c34 smbus interface ssmbaddr2 i c33 ssmbaddr3 i d33 ssmbaddr5 i d32 ssmbclk i/0 h28 ssmbdat i/o j27 swmode0 i an4 system swmode1 i ap4 swmode2 i an5 swmode3 i am5 v dd core, v dd i/o, v dd pea , v dd peha, v dd peta see table 25 for a listing of power pins. v ss see table 26 for a listing of ground pins. signal name i/o type location signal category table 28 pes34h16g2 alphabetical signal list (part 7 of 7)
50 of 54 november 28, 2011 idt 89HPES34H16G2 data sheet pes34h16g2 pinout ? top view 1 2 3 4 5 6 7 8 9 101112 1314 1516 a b 17 18 19 20 21 22 23 24 25 26 c d e f g h j k l m n p r t u v w y aa ab ac ad ae af 27 28 29 30 31 32 33 34 ag ah aj ak al am an ap a b c d e f g h j k l m n p r t u v w y aa ab ac ad ae af ag ah aj ak al am an ap 12345678910111213141516 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 vss (ground) v dd core (power) v dd i/o (power) v dd peta (transmitter power) v dd pea (analog power) v dd peha (high analog power) signals no connect x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x xx x x xx xx x x x x x x xx x x xx x x x x x x x x x x xx x x x x x x x x x x x xx x x x x x x x x x x x x x x x xx x x x x x xx x x xx x x xx x xx x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x
51 of 54 november 28, 2011 idt 89HPES34H16G2 data sheet pes34h16g2 package drawing ? 1156-pin bl1156/br1156
52 of 54 november 28, 2011 idt 89HPES34H16G2 data sheet pes34h16g2 package drawing ? page two
53 of 54 november 28, 2011 idt 89HPES34H16G2 data sheet revision history january 21, 2010 : publication of final data sheet. march 30, 2011 : in table 14, added v dd peta to footnote #1. november 28, 2011 : added new tables 21 and 22, smbus characterization and timing.
54 of 54 november 28, 2011 idt 89HPES34H16G2 data sheet corporate headquarters 6024 silver creek valley road san jose, ca 95138 for sales: 800-345-7015 or 408-284-8200 fax: 408-284-2775 www.idt.com for tech support: email: ssdhelp@idt.com phone: 408-284-8208 ? ordering information valid combinations 89h34h16g2zbbl 1156-ball fcbga package, commercial temperature 89h34h16g2zbblg 1156-ball green fcbga package, commercial temperature 89h34h16g2zbbli 1156-ball fcbga package, industrial temperature 89h34h16g2zbblgi 1156-ball green fcbga package, industrial temperature 89h34h16g2zcbl 1156-ball fcbga package, commercial temperature 89h34h16g2zcblg 1156-ball green fcbga package, commercial temperature 89h34h16g2zcbli 1156-ball fcbga package, industrial temperature 89h34h16g2zcblgi 1156-ball green fcbga package, industrial temperature nn a nnann aa a operating voltage product package temp range h product family 89 serial switching product 34h16 34-lane, 16-port 1.0v +/- 0.1v core voltage detail legend a = alpha character n = numeric character aa device revision an generation series g2 pcie gen 2 1156-ball fcbga bl 1156-ball fcbga, green blg blank commercial temperature (0c to +70c ambient) i industrial temperature (-40 c to +85 c ambient) zb zb revision zc zc revision

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